AM1705DPTP4 datasheet(47/165 Pages) TI1

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2000 N

Max PLL Lock Time =

where N = Pre-Divider Ratio

M = PLL Multiplier

AM1705

www.ti.com

SPRS657E – FEBRUARY 2010 – REVISED JUNE 2014

Table 6-4. Allowed PLL Operating Conditions

Default

No.

PARAMETER

MIN

MAX

UNIT

Value

PLLRST: Assertion time during

N/A

1000

N/A

initialization

Lock time: The time that the application

has to wait for the PLL to acquire locks

OSCIN

N/A

before setting PLLEN, after changing

cycles

PREDIV, PLLM, or OSCIN

PREDIV

/32

PLL input frequency

30 (if internal oscillator is used)

MHz

( PLLREF)

50 (if external clock source is used)

PLL multiplier values (PLLM) (1)

x20

x32

PLL output frequency. ( PLLOUT )

N/A

300

600

MHz

POSTDIV

/32

(1)

The multiplier values must be chosen such that the PLL output frequency (at PLLOUT) is between 300 and 600 MHz, but the frequency

going into the SYSCLK dividers (after the post divider) cannot exceed the maximum clock frequency defined for the device at a given

voltage operating point.

Peripheral Information and Electrical Specifications

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