PEB2256HT datasheet(99/490 Pages) INFINEON

99 / 490 page

FALC56 V1.2

PEB 2256

Functional Description E1

Data Sheet

2002-08-27

XL1/2 and if the transmit line current drops below the detection limit the high-impedance

state is cleared.

Two conditions are detected by the monitor: transmit line de-jitteredity (more than 31

consecutive zeros) indicated by FRS1.XLO and transmit line high current indicated by

FRS1.XLS. In both cases a transmit line monitor status change interrupt is provided.

Figure 25

Transmit Line Monitor Configuration (E1)

4.4.7

Transmit Signaling Controller (E1)

Similar to the receive signaling controller the same signaling methods and the same time

slot assignment is provided. The FALC56 performs the following signaling and data link

methods.

4.4.7.1

HDLC or LAPD access

The transmit signaling controller of the FALC56 performs the flag generation, CRC

generation, zero-bit stuffing and programmable idle code generation. Buffering of

transmit data is done in the 64 byte deep XFIFO. The signaling information is internally

multiplexed with the data applied to port XDI or XSIG.

In signaling controller transparent mode, fully transparent data transmission without

HDLC framing is performed. Optionally the FALC56 supports the continuous

transmission of the XFIFO contents.

The FALC56 offers the flexibility to insert data during certain time slots. Any

combinations of time slots can be programmed separately for the receive and transmit

direction if using HDLC channel 1. HDLC channel 2 and 3 support one programmable

time slot common for receive and transmit direction each.

ITS10936

Pulse

Shaper

Monitor

Line

TRI

XDATA

XL1

XL2

PEB2256HT bảng dữ liệu(PDF) 99 Page - Infineon Technologies AG