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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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PEB2256HT bảng dữ liệu(PDF) 84 Page - Infineon Technologies AG |
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PEB2256HT bảng dữ liệu(HTML) 84 Page - Infineon Technologies AG |
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84 / 490 page  FALC56 V1.2 PEB 2256 Functional Description E1 Data Sheet 84 2002-08-27 For transmit direction, contents of time slot 0 are additionally determined by the selected transparent mode. The CRC procedure is automatically invoked when the multiframe structure is enabled. CRC errors in the received data stream are counted by the 16-bit CRC Error Counter CEC (one error per submultiframe, maximum). Additionally a CRC4 error interrupt status ISR0.CRC4 is generated if enabled by IMR0.CRC4. All CRC bits of one outgoing submultiframe are automatically inverted in case a CRC error is flagged for the previous received submultiframe. This function is enabled by bit RC0.CRCI. Setting of bit RC0.XCRCI inverts the CRC bits before transmission to the distant end. The function of RC0.XCRCI and RC0.CRCI are logically ored. 4.2.3.1 Synchronization Procedure Multiframe alignment is assumed to have been lost if doubleframe alignment has been lost (flagged on status bit FRS0.LFA). The rising edge of this bit causes an interrupt. The multiframe resynchronization procedure starts when Doubleframe alignment has been regained which is indicated by an interrupt status bit ISR2.FAR. For Doubleframe synchronization refer to section Doubleframe Format. It is also be invoked by the user by setting • bit FMR0.FRS for complete doubleframe and multiframe resynchronization • bit FMR1.MFCS for multiframe resynchronization only. The CRC checking mechanism is enabled after the first correct multiframe pattern has been found. However, CRC errors are not counted in asynchronous state. Table 19 Transmit Transparent Mode (CRC Multiframe E1) Transmit Transparent Source for enabled by Framing + CRC A-Bit S a-Bits E-Bits – XSP.TT0 TSWM.TSIF TSWM.TSIS TSWM.TRA TSWM.TSA(8:4) (int. gen.) via pin XDI 1) via pin XDI via pin XDI (int. gen.) (int. gen.) 1) pin XDI or XSIG or XFIFO buffer (signaling controller) XSW.XRA 2) via pin XDI XSW.XRA 1) XSW.XRA 1) via pin XDI XSW.XRA 1) 2) Automatic transmission of the A-bit is selectable XSW.XY0 … 4 3) via pin XDI XSW.XY0 … 42) XSW.XY0 … 42) XSW.XY0 … 42) via pin XDI 3) The S a-bit register XSA(8:4) can be used optionally XSP.XS13/XS15 4) via pin XDI (int. generated) via pin XDI XSP.XS13/XS15 3) XSP.XS13/XS15 3) 4) Additionally, automatic transmission of submultiframe error indication is selectable |
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