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PEB2256HT bảng dữ liệu(PDF) 43 Page - Infineon Technologies AG

tên linh kiện PEB2256HT
Giải thích chi tiết về linh kiện  E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
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FALC56 V1.2
PEB 2256
Pin Descriptions
Data Sheet
43
2002-08-27
67
68
69
70
D6
A6
B5
D5
RPA
RPB
RPC
RPD
O
Frame Synchronous Pulse (RFSP)
PC(1:4).RPC(2:0) = 111
Active low framing pulse derived from the
received PCM route signal (line side, RCLK).
During loss of synchronization (bit
FRS0.LFA = 1), this pulse is suppressed (not
influenced during alarm simulation).
Pulse frequency: 8 kHz
Pulse width: 488 ns (E1) or 648 ns (T1/J1).
System Interface Transmit
56
D8
XDI
I
Transmit Data In
Transmit data received from the system
highway. Latching of data is done with rising or
falling transitions of SCLKX according to bit
SIC3.RESX.
The delay between the beginning of time slot 0
and the initial edge of SCLKX (after SYPX
goes active) is determined by the registers
XC(1:0).
In higher (more than 1.544/2.048 Mbit/s) data
rates sampling of data is defined by bits
SIC2.SICS(2:0).
64
C6
SCLKX
I + PU
System Clock Transmit
Working clock for the transmit system interface
with a frequency of 16.384/8.192/4.096/2.048
in E1 mode and 16.384/8.192/4.096/2.048
MHz (SIC2.SSC2 = 0) or 12.352/6.176/3.088/
1.544 MHz (SIC2.SSC2 = 1) in T1/J1 mode.
Table 4
Pin Definitions - System Interface (cont’d)
Pin
No.
Ball
No.
Symbol
Input (I)
Output (O)
Supply (S)
Function



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