công cụ tìm kiếm bảng dữ liệu linh kiện điện tử
  Vietnamese  ▼
ALLDATASHEET.VN

X  

Preview PDF HTML

PEB2256HT bảng dữ liệu(PDF) 37 Page - Infineon Technologies AG

tên linh kiện PEB2256HT
Giải thích chi tiết về linh kiện  E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
PDF  490 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
nhà sản xuất  INFINEON [Infineon Technologies AG]
Trang chủ  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

PEB2256HT bảng dữ liệu(HTML) 37 Page - Infineon Technologies AG

Back Button PEB2256HT Datasheet HTML 33Page - Infineon Technologies AG PEB2256HT Datasheet HTML 34Page - Infineon Technologies AG PEB2256HT Datasheet HTML 35Page - Infineon Technologies AG PEB2256HT Datasheet HTML 36Page - Infineon Technologies AG PEB2256HT Datasheet HTML 37Page - Infineon Technologies AG PEB2256HT Datasheet HTML 38Page - Infineon Technologies AG PEB2256HT Datasheet HTML 39Page - Infineon Technologies AG PEB2256HT Datasheet HTML 40Page - Infineon Technologies AG PEB2256HT Datasheet HTML 41Page - Infineon Technologies AG Next Button
Zoom Inzoom in Zoom Outzoom out
 37 / 490 page
background image
FALC56 V1.2
PEB 2256
Pin Descriptions
Data Sheet
37
2002-08-27
77
C3
CLK2
O + PU
System Clock of DCO-X
Output of the de-jittered system clock
generated by the DCO-X circuit. Frequency
selection is done by setting control bits in PC5/
6.
E1: 16.384 MHz, 8.192 MHz, 4.096 MHz or
2.048 MHz
T1/J1: 12.352 MHz, 6.176 MHz, 3.088 MHz or
1.544 MHz
After reset this output is inactive and internally
pulled high.
Note: If DCO-X is not used, no clock is output
on pin CLK2 (SIC1.XBS(1:0) = 00 and
CMR1.DXJA = 1; buffer bypass and no
jitter attenuation)
78
B3
SEC
I + PU
One-Second Timer Input
A pulse with logical high level for at least two
2.048-MHz cycles triggers the internal one-
second timer. After reset this pin is configured
to be an input. If not connected, an internal
pullup transistor ensures high input level (see
register GPC1).
O
One-Second Timer Output
Activated high every second for two 2.048-
MHz clock cycles.
FSC
O
Optionally an 8-kHz frame synchronization
pulse is output via this pin. The
synchronization pulse is active high or low for
one 2.048/1.544-MHz cycle (pulse width = 488
ns for E1and 648 ns or T1/J1).
Table 3
Pin Definitions - Clock Generation (cont’d)
Pin
No.
Pin
No.
Symbol
Input (I)
Output (O)
Supply (S)
Function



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


bảng dữ liệu tải về

Go To PDF Page


Link URL



Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không?  [ DONATE ] 

Alldatasheet là   |   Quảng cáo   |   Liên lạc với chúng tôi   |   Chính sách bảo mật   |   Liên kết đến bảng dữ liệu    |   Trao đổi link   |   Tìm kiếm theo nhà sản xuất
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com