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PEB2256HT bảng dữ liệu(PDF) 49 Page - Infineon Technologies AG

tên linh kiện PEB2256HT
Giải thích chi tiết về linh kiện  E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
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FALC56 V1.2
PEB 2256
Pin Descriptions
Data Sheet
49
2002-08-27
Note: oD = open drain output
PU = input or input/output comprising an internal pullup device
To override the internal pullup by an external pulldown, a resistor value of 22 k
Ω
is recommended.
The pullup devices are activated during reset, this means their state is undefined
until the reset signal has been applied.
Unused pins containing pullups can be left open.
Unused Pins
19
20
74
80
A4
B2
E5
H1
H2
N.C.
not connected, to be left open for compatibility
with future products.
Boundary Scan/Joint Test Access Group (JTAG)
14
F1
TRS
I + PU
Test Reset for Boundary Scan
(active low). If not connected, an internal pullup
transistor ensures high input level.
If the JTAG boundary scan is not used, this pin
must be connected to RES or V
SS.
15
G1
TDI
I + PU
Test Data Input for Boundary Scan
If not connected an internal pullup transistor
ensures high input level.
16
F2
TMS
I + PU
Test Mode Select for Boundary Scan
If not connected an internal pullup transistor
ensures high input level.
17
G3
TCK
I + PU
Test Clock for Boundary Scan
If not connected an internal pullup transistor
ensures high input level.
18
G2
TDO
O
Test Data Output for Boundary Scan
Table 5
Pin Definitions - Miscellaneous (cont’d)
Pin
No.
Ball
No.
Symbol
Input (I)
Output (O)
Supply (S)
Function



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