công cụ tìm kiếm bảng dữ liệu linh kiện điện tử
  Vietnamese  ▼
ALLDATASHEET.VN

X  

STM32F446MC bảng dữ liệu(PDF) 110 Page - STMicroelectronics

tên linh kiện STM32F446MC
Giải thích chi tiết về linh kiện  8- to 14-bit parallel camera interface up to 54 Mbytes
PDF  201 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
Trang chủ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32F446MC bảng dữ liệu(HTML) 110 Page - STMicroelectronics

Back Button STM32F446MC Datasheet HTML 106Page - STMicroelectronics STM32F446MC Datasheet HTML 107Page - STMicroelectronics STM32F446MC Datasheet HTML 108Page - STMicroelectronics STM32F446MC Datasheet HTML 109Page - STMicroelectronics STM32F446MC Datasheet HTML 110Page - STMicroelectronics STM32F446MC Datasheet HTML 111Page - STMicroelectronics STM32F446MC Datasheet HTML 112Page - STMicroelectronics STM32F446MC Datasheet HTML 113Page - STMicroelectronics STM32F446MC Datasheet HTML 114Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 110 / 201 page
background image
Electrical characteristics
STM32F446xC/E
110/201
DocID027107 Rev 5
6.3.12
PLL spread spectrum clock generation (SSCG) characteristics
The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic
interferences (see Table 52: EMI characteristics). It is available only on the main PLL.
Equation 1
The frequency modulation period (MODEPER) is given by the equation below:
MODEPER
round fPLL_IN
4fMod
×
()
[]
=
Table 45. PLLISAI characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fPLLSAI_IN
PLLSAI input clock(1)
-0.95(2)
12.10
MHz
fPLLSAI_OUT
PLLSAI multiplier output clock
-
-
-
216
MHz
fVCO_OUT
PLLSAI VCO output
-
100
-
432
MHz
tLOCK
PLLSAI lock time
VCO freq = 100 MHz
75
-
200
µs
VCO freq = 432 MHz
100
-
300
Jitter(3)
Main SAI clock jitter
Cycle to cycle at
12.288 MHz on
48KHz period,
N=432, R=5
RMS
-
90
-
-
peak
to
peak
-
±280
-
ps
Average frequency of
12.288 MHz
N = 432, R = 5
on 1000 samples
-90
-
ps
FS clock jitter
Cycle to cycle at 48 KHz
on 1000 samples
-400
-
ps
IDD(PLLSAI)(4)
PLLSAI power consumption on
VDD
VCO freq = 100 MHz
VCO freq = 432 MHz
0.15
0.45
-
0.40
0.75
mA
IDDA(PLLSAI)(4)
PLLSAI power consumption on
VDDA
VCO freq = 100 MHz
VCO freq = 432 MHz
0.30
0.55
-
0.40
0.85
mA
1. Take care of using the appropriate division factor M to have the specified PLL input clock values.
2. Guaranteed by design.
3. Value given with main PLL running.
4. Guaranteed based on test during characterization.
Table 46. SSCG parameters constraint
Symbol
Parameter
Min
Typ
Max(1)
Unit
fMod
Modulation frequency
-
-
10
KHz
md
Peak modulation depth
0.25
-
2
%
MODEPER * INCSTEP
-
-
-
215
−1-
1. Guaranteed by design.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


bảng dữ liệu tải về

Go To PDF Page


Link URL



Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không?  [ DONATE ] 

Alldatasheet là   |   Quảng cáo   |   Liên lạc với chúng tôi   |   Chính sách bảo mật   |   Liên kết đến bảng dữ liệu    |   Trao đổi link   |   Tìm kiếm theo nhà sản xuất
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com