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SPEAR320S bảng dữ liệu(PDF) 96 Page - STMicroelectronics

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SPEAR320S bảng dữ liệu(HTML) 96 Page - STMicroelectronics

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Timing requirements
SPEAr320S
96/113
Doc ID 022508 Rev 2
5.14
SD timing characteristics
Figure 29.
SD timing waveform
Note:
In full-speed mode, the frequency is 24 MHZ (41.6 ns). The data is launched at the falling
edge of the 24 MHZ clock and captured on the clock’s rising edge (the effective available
time is always 20.8 ns)
Table 71.
SD timing requirements (high-speed mode, 48 MHz)
Symbol
Description
Min
Max
Unit
tCK
SD_CLK clock period
20.8
–
ns
tD
SD_CLK to SD output delay
-1.60
10
tS
Setup time requirement for SD inputs
7.35
tH
Hold time requirement for SD inputs
0.19
Table 72.
SD timing requirements (full-speed mode, 24 MHz)
Symbol
Description
Min
Max
Unit
tCK
SD_CLK clock period
41.6
–
ns
tck-half
SD_CLK half period
20.8
tD
SD_CLK to SD output delay
-0.40
10
tS
Setup time requirement for SD inputs
7.35
tH
Hold time requirement for SD inputs
0.19
tCK
SD_CLK
SD_DAT#
SD_WP
SD_CMD
SD_LED
SD_CD
SD_DAT#
(input)
tS
tH
D
t



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