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SPEAR320S bảng dữ liệu(PDF) 81 Page - STMicroelectronics

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SPEAR320S bảng dữ liệu(HTML) 81 Page - STMicroelectronics

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SPEAr320S
Timing requirements
Doc ID 022508 Rev 2
81/113
5.5
DDR2/LPDDR timing characteristics
The timing parameters listed below are defined by the JEDEC Standard for DDR memories.
DDR memories whose parameters are within the ranges defined in Table 53, Table 54 and
Table 55 can be interfaced with SPEAr320S.
Read cycle timing apply to DQS and DQ input to SPEAr. Write cycle timings refer to DQS
and DQ output to SPEAr.
The timing characterization is performed assuming an output load capacitance of 10 pF on
all the DDR pads.
5.5.1
DDR2/LPDDR read cycle timing characteristics
Figure 10.
DDR2/LPDDR read cycle waveform
Table 53.
DDR2/LPDDR read cycle timing requirements
Symbol
Description
Min
Max
Unit
tCK
DDR_MEM_CLKP/CLKN cycle time when
interfacing DDR2 memory
3
ns
LPDDR DDR_MEM_CLKP/CLKN cycle
time when interfacing LPDDR memory
6
tDQSQ
DQS to DQ input setup time
0
0.25tCK+0.4
tQH
DQS to DQ input hold time
0.25tCK+0.7
0.5tCK
tDQSQ
tQH
tQH
tDQSQ
tDQSQ
DDR_MEM_DQS_#
DDR_MEM_DQ_#
DDR_MEM_CLKP/
DDR_MEM_CLKN
tCK



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