MEC1322 datasheet(365/456 Pages) MICROCHIP

365 / 456 page

 2014 - 2015 Microchip Technology Inc.

DS00001719D-page 365

MEC1322

32.7

Power, Clocks and Reset

This section defines the Power, Clock, and Reset parameters of the block.

32.7.1

POWER DOMAINS

32.7.2

CLOCK INPUTS

32.7.3

RESETS

32.8

Interrupts

There are no interrupts generated from this block.

32.9

Low Power Modes

The Trace FIFO Debug Port (TFDP) may be put into a low power state by the chip’s Power, Clocks, and Reset (PCR)

circuitry.

32.10 Description

The TFDP is a unidirectional (from processor to external world) two-wire serial, byte-oriented debug interface for use

by processor firmware to transmit diagnostic information.

The TFDP consists of the Debug Data Register, Debug Control Register, a Parallel-to-Serial Converter, a Clock/Control

Interface and a two-pin external interface (TFDP Clk, TFDP Data).

FIGURE 32-2:

BLOCK DIAGRAM OF TFDP DEBUG PORT

TABLE 32-2:

POWER SOURCES

Name

Description

VCC1

This power well sources all of the registers and logic in this block.

TABLE 32-3:

CLOCK INPUTS

Name

Description

48 MHz Ring Oscillator

This clock input is used to derive the TFDP Clk.

TABLE 32-4:

RESET SIGNALS

Name

Description

VCC1_RESET

This reset signal resets all of the registers and logic in this block.

Data

PARALLEL-TO-SERIAL

CONVERTER

CLOCK/CONTROL

INTERFACE

WRITE_COMPLETE

TFDP_DAT

TFDP_CLK

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