MEC1322 datasheet(350/456 Pages) MICROCHIP

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MEC1322

DS00001719D-page 350

 2014 - 2015 Microchip Technology Inc.

2PE

Parity Error

When receiving data, the parity bit is clocked in on the falling edge of

the 10th CLK edge. If the channel is configured to expect either even

or odd parity and the 10th bit is contrary to the expected parity, then

the PE and REC_TIMEOUT bits are set following the falling edge of

the 10th CLK edge and an interrupt is generated.

R/WC

VCC1_R

ESET

1 REC_TIMEOUT

Receive Timeout

Following assertion of the REC_TIMEOUT bit, the channel’s CLK

line is automatically pulled low for a minimum of 300us until the PS/2

status register is read. Under PS2 automatic operation, PS2_EN is

set, this bit is set on one of three receive error conditions:

When the receiver bit time (the time between falling edges) exceeds

300μs.

If the time from the first bit (start) to the 10th bit (parity) exceeds

2ms.

On a receive parity error along with the Parity Error (PE) bit.

On a receive framing error due to an incorrect STOP bit along with

the framing error (FE) bit.

A low to high transition on this bit generates a PS2 Activity interrupt.

R/WC

VCC1_R

ESET

0 RDATA_RDY

Receive Data Ready

Under normal operating conditions, this bit is set following the falling

edge of the 11th clock given successful reception of a data byte from

the PS/2 peripheral (i.e., no parity, framing, or receive time-out

errors) and indicates that the received data byte is available to be

read from the Receive Register. This bit may also be set in the event

that the PS2_EN bit is cleared following the 10th CLK edge.

Reading the Receive Register clears this bit.

A low to high transition on this bit generates a PS2 Activity interrupt.

VCC1_R

ESET

Offset

08h

Bits

Description

Type

Default

Reset

Event

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