MEC1322 datasheet(289/456 Pages) MICROCHIP

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DS00001719D-page 289

MEC1322

25.11.2

PWMX COUNTER OFF TIME REGISTER

25.11.3

PWMX CONFIGURATION REGISTER

Offset

04h

Bits

Description

Type

Default

Reset

Event

31:16 Reserved

15:0 PWMX_COUNTER_OFF_TIME

This field determine both the frequency and duty cycle of the PWM

signal.

When this field is set to zero, the PWM_OUTPUT is held high (Full

On).

R/W

FFFFh

VCC1_R

ESET

Offset

08h

Bits

Description

Type

Default

Reset

Event

31:7 Reserved

6:3 CLOCK_PRE_DIVIDER

The Clock source for the 16-bit down counter (see PWMx Counter

ON Time Register and PWMx Counter OFF Time Register) is deter-

mined by bit D1 of this register. The Clock source is then divided by

the value of Pre-Divider+1 and the resulting signal determines the

rate at which the down counter will be decremented. For example, a

Pre-Divider value of 1 divides the input clock by 2 and a value of 2

divides the input clock by 3. A Pre-Divider of 0 will disable the Pre-

Divider option.

R/W

0000b

VCC1_R

ESET

2INVERT

1= PWM_OUTPUT ON State is active low

0=PWM_OUTPUT ON State is active high

R/W

VCC1_R

ESET

1 CLOCK_SELECT

This bit determines the clock source used by the PWM duty cycle

and frequency control logic.

1=CLOCK_LOW

0=CLOCK_HIGH

R/W

VCC1_R

ESET

0 PWM_ENABLE

1=Enabled (default)

0=Disabled (gates clocks to save power)

Note:

When the PWM enable bit is set to 0 the internal counters

are reset and the internal state machine is set to the OFF

state. In addition, the PWM_OUTPUT signal is set to the

inactive state as determined by the Invert bit. The PWMx

Counter ON Time Register and PWMx Counter OFF

Time Register are not affected by the PWM enable bit

and may be read and written while the PWM enable bit is

R/W

VCC1_R

ESET

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