MEC1322 datasheet(274/456 Pages) MICROCHIP

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MEC1322

DS00001719D-page 274

 2014 - 2015 Microchip Technology Inc.

22.11.2

PHYSICAL INTERFACE

The SMBus Interface has two physical ports, selected by the PORT SEL [3:0] bits in the Configuration Register as

described in Ref [1].

Note 1:

SMBus controller 0 uses port 0 and port 1. SMBus controllers 1-3 use port 0.

The buffer type for these pins must be configured as open-drain outputs in the GPIO Configuration registers

associated with the GPIO signals that share the ports.

22.12 SMBus Registers

The registers listed in the SMBus Core Register Summary table in the SMBus Controller Core Interface specification

(Ref [1]) are for a single instance of the SMBus Controller Core. The addresses of each register listed in this table are

defined as a relative offset to the host “Base Address” defined in the following table:

Note 22-1

The Base Address indicates where the first register can be accessed in a particular address space

for a block instance.

TABLE 22-7:

EC-ONLY REGISTER BASE ADDRESS TABLE

Block Instance

Instance

Number

Host

Address Space

Base Address (

Note 22-1)

SMBus Controller

32-bit internal

address space

4000_1800h

SMBus Controller

32-bit internal

address space

4000_AC00h

SMBus Controller

32-bit internal

address space

4000_B000h

SMBus Controller

32-bit internal

address space

4000_B400h

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