XC164CS datasheet(23/71 Pages) INFINEON

23 / 71 page

XC164

Derivatives

Functional Description

Data Sheet

V2.1, 2003-06

optimization, the branch target prediction, allows eliminating the execution time of

branch instructions if the prediction was correct.

The CPU has a register context consisting of up to three register banks with 16 wordwide

GPRs each at its disposal. One of these register banks is physically allocated within the

on-chip DPRAM area. A Context Pointer (CP) register determines the base address of

the active register bank to be accessed by the CPU at any time. The number of register

banks is only restricted by the available internal RAM space. For easy parameter

passing, a register bank may overlap others.

A system stack of up to 32 Kwords is provided as a storage for temporary data. The

system stack can be allocated to any location within the address space (preferably in the

on-chip RAM area), and it is accessed by the CPU via the stack pointer (SP) register.

Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack

pointer value upon each stack access for the detection of a stack overflow or underflow.

The high performance offered by the hardware implementation of the CPU can efficiently

be utilized by a programmer via the highly efficient XC164 instruction set which includes

the following instruction classes:

– Standard Arithmetic Instructions

– DSP-Oriented Arithmetic Instructions

– Logical Instructions

– Boolean Bit Manipulation Instructions

– Compare and Loop Control Instructions

– Shift and Rotate Instructions

– Prioritize Instruction

– Data Movement Instructions

– System Stack Instructions

– Jump and Call Instructions

– Return Instructions

– System Control Instructions

– Miscellaneous Instructions

The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes

and words. A variety of direct, indirect or immediate addressing modes are provided to

specify the required operands.

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