XC164CS datasheet(66/71 Pages) INFINEON

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XC164

Derivatives

Timing Parameters

Data Sheet

V2.1, 2003-06

Variable Memory Cycles

External bus cycles of the XC164 are executed in five subsequent cycle phases (AB, C,

D, E, F). The duration of each cycle phase is programmable (via the TCONCSx

registers) to adapt the external bus cycles to the respective external module (memory,

peripheral, etc.).

This table provides a summary of the phases and the respective choices for their

duration.

Note: The bandwidth of a parameter (minimum and maximum value) covers the whole

operating range (temperature, voltage) as well as process variations. Within a

given device, however, this bandwidth is smaller than the specified range. This is

also due to interdependencies between certain parameters. Some of these

interdependencies are described in additional notes (see standard timing).

Table 18

Programmable Bus Cycle Phases (see timing diagrams)

Bus Cycle Phase

Parameter

Valid Values Unit

Address setup phase, the standard duration of this

phase (1

…2 TCP) can be extended by 0 …3 TCP if

the address window is changed

tpAB

…2 (5)

TCP

Command delay phase

tpC

…3

TCP

Write Data setup / MUX Tristate phase

tpD

…1

TCP

Access phase

tpE

…32

TCP

Address / Write Data hold phase

tpF

…3

TCP

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