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RM0319 bảng dữ liệu(PDF) 290 Page - STMicroelectronics

tên linh kiện RM0319
Giải thích chi tiết về linh kiện  SPEAr320S architecture and functionality
PDF  368 Pages
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
Trang chủ  http://www.st.com
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RM0319 bảng dữ liệu(HTML) 290 Page - STMicroelectronics

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JPEG codec accelerator (JPGC)
RM0319
290/368
Doc ID 022640 Rev 3
26.4.4
FIFO buffers
These two First-in First-out buffers have a word width of 32 bits, and a depth of 8 words.
FIFOs are used by the Codec Controller to bufferize the flow of data incoming to (FIFO In)
and outcoming from (FIFO out) the Codec Core. Each FIFO is accessed by reading/writing
always from/to the same address.
26.4.5
Internal memories
These memories have to be programmed, before the encoding process can start, with the
tables needed by the baseline JPEG algorithm (see ISO/IEC 10918-1).
Up to four quantization tables are used for both encoding and decoding. DHTMem and
HuffEnc memories are used for encoding. HuffMin, HuffBase and HuffSymb memories are
used for decoding.



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