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RM0319

Extended general purpose I/O (PL_GPIO)

Doc ID 022640 Rev 3

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Extended general purpose I/O (PL_GPIO)

This chapter focuses on PL_GPIO functionality and operation.

For technical details about the programmable registers related to the PL_GPIO, refer to the

RAS registers in the following companion document:

●

RM0321: SPEAr320S address map and registers

23.1

Overview

Extended general purpose I/Os are software programmable input/output pins through an

AHB slave interface. They configure all PL_GPIO and PL_CLK signals of SPEAr320S,

writing data to external interfaces or receiving data/interrupts from external interfaces.

Interrupt trigger polarity is programmable as rising or falling edge.

Figure 95.GPIO block diagram

23.2

Configuration

To use PL_GPIO pins for general purpose I/O, the pins must be configured as follows:

Check that RAS function is selected for the corresponding set of PL_GPIO pins in the

RAS_Select_Register

Configure the corresponding bit for the PL_GPIO pin in the GPIO select register x.

Enable the PLGPIO pin in input or output mode by programming the corresponding bit

in the GPIO enable register.

In input mode:

The value of the pin can be read from the GPIO input register

In output mode:

Data can be output on the pin by writing to the GPIO output register.

GPIO Block

GPIO IN

GPIO OUT

GPIO EN

AHB

Interface

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