RM0319 datasheet(241/368 Pages) STMICROELECTRONICS

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RM0319

Synchronous serial ports (SSP)

Doc ID 022640 Rev 3

241/368

Programming sequence for generating chip select (SSP0_CS2, SSP0_CS3, SSP0_CS4 -

not required for SSP0_SS0);

Program control bits [12:11] in the RAS Select Register to enable SPI_enhanced

mode.

Program the GPIODATA register bits [7:6] with the above values from Table 69 to select

one of the SSP0_CSx pins.

Program SSP0 in master mode.

Enable transmit-receive

Follow steps 2-4 if a different slave is to be selected.

Note:

All current transmission/reception must end before enabling CS for a different slave.

Enabling "Enhanced mode for SSP0" will disable any other functionality on PL_GPIO[36],

PL_GPIO[35], PL_GPIO[34] EXCEPT SSP0_CSx.

18.5.2

Enabling SSP operation

To enable SSP, you can either:

●

prime the transmit FIFO, by writing up to eight 16-bit values when the SSP is disabled,

-or-

●

allow the transmit FIFO service request to interrupt the CPU.

Once enabled, transmission or reception of data begins on the SSPx MOSI and

SSPx_MISO pins.

Clock ratios

There is a constraint on the ratio of the frequencies of PCLK to SSPCLK. The frequency of

SSPCLK must be less than or equal to that of PCLK. This ensures that control signals from

the SSPCLK domain to the PCLK domain are certain to get synchronized before one frame

duration:

FSSPCLK <= FPCLK.

In the slave operation, the SSPCLKIN signal from the external master is double

synchronized and then delayed to detect an edge. It takes three SSPCLKs to detect an edge

on SSPCLKIN. SSPTXD has less setup time to the falling edge of SSPCLKIN on which the

master is sampling the line. The setup and hold times on SSPRXD with reference to

SSPCLKIN must be more conservative to ensure that it is at the right value when the actual

sampling occurs within the SSPMS. To ensure correct device operation, SSPCLK must be at

least 12 times faster than the maximum expected frequency of SSPCLKIN.

Table 69.

External CS selection

GPIODATA register bit [7]

output value

GPIODATA register bit [6]

output value

External slave select pin

SSP0_SS0

SSP0_CS2

SSP0_CS3

SSP0_CS4

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