RM0319 datasheet(121/368 Pages) STMICROELECTRONICS

121 / 368 page

RM0319

USB 2.0 Device ports (UDC)

Doc ID 022640 Rev 3

121/368

Figure 35.

RxFIFO implementation

Upon receiving an out packet, UTLI strobes this data into the data FIFO (37 bit wide), and

the UDC sends a status bit indicating whether or not the data was received without errors. If

data reception was error-free, the UTLI confirms the data in the RxFIFO by writing the

relevant endpoint number and associated flag into the address FIFO. In contrast, if data was

received with errors, the receive FIFO controller rolls back the data FIFO pointers as if

nothing had been received.

Then, when an external AHB master tries to access the packet received for a particular out

endpoint, at first it must read the relevant endpoint status register to determine the number

of bytes to be transferred, before to start the appropriate AHB transfers with an appropriate

HSIZE (for instance, 32, 16 or 8).

Note:

Any attempt to write the RxFIFO via the AHB interface results in an AHB error.

The RxFIFO also requires a confirming signal when a packet is written to or read from it.

This confirmation is used by the receive FIFO controller to propagate pointer information

from one domain to another and to calculate different RxFIFO status signals.

Address

Data

32 bits wide

37 bits wide

Addrss FIFO

(Implemented in Regiters)

Data FIFO

(Implemented in RAM)

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