RM0312 datasheet(82/275 Pages) STMICROELECTRONICS

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General purpose I/O ports (GPIO)

RM0312

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DocID022352 Rev 3

10.9.5

Port x control register 2 (Px_CR2)

Address offset: 0x04

Reset value: 0x00

10.9.6

GPIO register map and reset values

Each GPIO port has five registers mapped as shown in Table 21. Refer to the register map

in the corresponding datasheet for the base address for each port.

Note:

At reset state, all ports are input floating. Exceptions are indicated in the pin description

table of the corresponding datasheet.

654

3210

C27

C26

C25

C24

C23

C22

C21

C20

Bits 7:0 C2[7:0]: Control bits

These bits are set and cleared by software. They select different functions in input mode and output

mode. In input mode, the CR2 bit enables the interrupt capability if available. If the I/O does not have

interrupt capability, setting the CR2 bit has no effect. In output mode, setting the bit increases the

speed of the I/O. This applies to ports with O3 and O4 output types (see pin description table).

– In input mode (DDR = 0):

0: External interrupt disabled

1: External interrupt enabled

– In output mode (DDR = 1):

0: Output speed up to 2 MHz

1: Output speed up to 10 MHz

Table 21. GPIO register map

Address

offset

name

7654321

0x00

Px_ODR

Reset value

ODR7

ODR6

ODR5

ODR4

ODR3

ODR2

ODR1

ODR0

0x01

Px_IDR

Reset value

IDR7

IDR6

IDR5

IDR4

IDR3

IDR2

IDR1

IDR0

0x02

Px_DDR

Reset value

DDR7

DDR6

DDR5

DDR4

DDR3

DDR2

DDR1

DDR0

0x03

Px_CR1

Reset value

C17

C16

C15

C14

C13

C12

C11

C10

0x04

Px_CR2

Reset value

C27

C26

C25

C24

C23

C22

C21

C20

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