AN4192 datasheet(24/47 Pages) STMICROELECTRONICS

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Low-side FET selection

AN4192

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Doc ID 023820 Rev 1

Figure 25.

High-CRSS LS FET phase node waveform @ 80 A

As shown in previous images, the “high-CRSS” device has lower phase node spike (18.8 V

vs. 30.7 V of the low-CRSS FET).

The right value of the Miller capacitance allows a good improvement on the LS switching

behavior, reducing the maximum phase node spike, without detrimental effects on other

device features (shoot-through issue, LS gate-source bouncing). Increasing the CRSS value,

we obtain some important effects on LS performance:

Low-side FET intrinsic slow-down.

“Intrinsic and VDS linked” R-C snubber (Rgate - CRSS) effect (Rgate is the total gate

resistance): at HS turn-on, the Miller capacitance is in series with the total gate

resistance, creating an “intrinsic” snubber. The capacitive effect is linked to the

applied VDS across the LS FET.

Higher CRSS value causes a “sub-threshold” conduction, which helps to divert the

load current from the body diode (during the deadtime) to the channel, reducing

the reverse recovery process stresses.

3.3

LS body-drain diode Qrr (reverse recovery charge)

During the deadtime, when both HS and LS FETs are in the OFF-state, the load current

cannot immediately drop to zero so it flows through the LS body-drain diode, that is forward

biased (VDS,LS = -0.7 V). In Figure 26, the red arrow represents the load current flowing

through the body diode. The charge stored in the body diode depends mainly on the load

current amplitude and the deadtime length. This charge must be removed before the LS can

sustain voltage (OFF-state). In Figure 27, from T0 to T1, the body diode current becomes

negative, depleting the excess charge stored. In this period, the LS body diode acts as the

energy source, delivering energy to other components. When the stored charge is totally

AM16469V1

AN4192 bảng dữ liệu(PDF) 24 Page - STMicroelectronics