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AN4192 bảng dữ liệu(PDF) 18 Page - STMicroelectronics |
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AN4192 bảng dữ liệu(HTML) 18 Page - STMicroelectronics |
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18 / 47 page ![]() High-side MOSFET selection AN4192 18/47 Doc ID 023820 Rev 1 Figure 18. Phase node waveform - standard configuration Figure 19. Phase node waveform - HS asymmetric gate drive configuration Looking at the previous waveforms, due to the reduced HS turn-on speed, there is a clear reduction of the phase node spike (21 V vs. 24.4 V), when the HS asymmetric gate drive is used. Moreover, the LS gate-source bouncing, induced at HS turn-on, is smoothed. Comparing the efficiency curves (Figure 20), the asymmetric gate drive has slightly better efficiency (+0.7% at full load). This can be explained considering that: 1. The HS turn-off resistor is smaller (1.8 Ω vs. 2.2 Ω) and consequently the switching losses at turn-off are lower. 2. Even if the HS turn-on resistor is bigger, the switching losses at turn-on are negligible. AM16462V1 AM16463V1 |
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