AN4192 datasheet(14/47 Pages) STMICROELECTRONICS

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High-side MOSFET selection

AN4192

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Doc ID 023820 Rev 1

In Figure 9 and 10, the HS turn-off waveforms of the two FETs are shown. Higher CGD

values reduce the HS VDS maximum spike (18.4 V vs. 23.1 V) and

(2.1 V/ns vs. 3.9 V/ns); furthermore, the VGS falling edge slope is slower (the Miller plateau

is more visible and VGS fall time is higher). Obviously, the main design rule is that VDS,HS

must be lower than the HS breakdown voltage (typically, VDS,HS(max) ≤0.8 * BVDS,HS to

increase MOSFET reliability).

The Miller capacitance value should be the correct trade-off between efficiency

improvement at high fSW (low QG,Sw and QGD) and HS maximum voltage stress reduction

(high QGD).

2.1

RDS(on) and conduction losses minimization

Considering a single-phase synchronous buck converter with a single HS device, the HS

conduction losses are shown in the following formula:

Equation 3

where D is the converter duty cycle, RDS(on) is the ON-state drain-source resistance,

evaluated at the operating temperature (T °C), and ID,HS is the HS drain current. As D is low

(0.1% - 0.2%), this term is not the most important in converter performance enhancement.

However, a slight efficiency enhancement can be noted at high output currents, when a

lower RDSon high-side FET is used.

Figure 11.

Single-phase synchronous buck converter schematic

In Figure 11, a single-phase synchronous buck converter schematic (VIN = 12 V, VOUT =

1.25 V, IOUT,MAX = 20 A, fSW = 270 kHz, 1 x HS, 1 x LS) is shown, where two different high-

side FETs (“high-side 5” and “high-side 6”) are compared with a fixed LS device. External

gate resistances are connected to HS (2.2

Ω) and LS (1.8 Ω) FETs. An RC snubber network

DS,HS

----------------------

HS,COND

DS on

() TI

D,HS

⋅

AM16455V1

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