STAC9704 datasheet(31/49 Pages) HYNIX

31 / 49 page

SigmaTel, Inc.

STAC9704/7

10/02/98

Table 17: Powerdown Status Register

BIT

FUNCTION

REF

VREF’s up to nominal level

ANL

Analog mixers, etc. ready

DAC

DAC section ready to playback data

ADC

ADC section ready to playback data

5. LOW POWER MODES

The STAC9704/7 is capable of operating at reduced power when no activity is required. The state of power

down is controlled by the Powerdown Register (26h). There are 7 commands of separate power down. The

power down options are listed in Table 18. The first three bits , PR0..PR2, can be used individually or in

combination with each other, and control power distribution to the ADC’s, DAC’s and Mixer. The last analog

power control bit, PR3, affects analog bias and reference voltages, and can only be used in combination with PR1,

PR2, and PR3. PR3 essentially removes power from all analog sections of the codec, and is generally only

asserted when the codec will not be needed for long periods. PR0 and PR1 control the PCM ADC’s and DAC’s

only. PR2 and PR3 do not need to be "set" before a PR4, but PR0 and PR1 must be "set" before PR4.

Table 18: Low Power Modes

GRP BITS

FUNCTION

PR0

PCM in ADC’s & Input Mux Powerdown

PR1

PCM out DACs Powerdown

PR2

Analog Mixer powerdown (Vref still on)

PR3

Analog Mixer powerdown (Vref off)

PR4

Digital Interface (AC-link) powerdown (extnl clk off)

PR5

Internal Clk disable

STAC9704 bảng dữ liệu(PDF) 31 Page - Hynix Semiconductor