STAC9704 datasheet(18/49 Pages) HYNIX

18 / 49 page

SigmaTel, Inc.

STAC9704/7

10/02/98

Figure 9: Start of an Audio Input Frame

SYNC

BIT_CLK

SDATA_IN

STAC9704 samples first SDATA_OUT bit of frame here

STAC9704 samples SYNC assertion here

Codec

Ready

slot1

slot2

End of previous audio frame

SDATA_IN's composite stream is MSB justified (MSB first) with all non-valid bit positions (for

assigned and/or unassigned time slots) stuffed with 0's by STAC9704/7. SDATA_IN data is sampled on

the falling edges of BIT_CLK.

3.1.2.1 Slot 1: Status Address Port

The status port is used to monitor status for STAC9704/7 functions including, but not limited

to, mixer settings, and power management.

Audio input frame slot 1’s stream echoes the control register index, for historical reference,

for the data to be returned in slot 2. (Assuming that slots 1 and 2 had been tagged “valid” by

STAC9704/7 during slot 0)

Status Address Port hit assignments:

Bit (19)

RESERVED

(Stuffed with 0)

Bit (18;12) Control Register Index

(Echo of register index for which data is being returned)

Bit (11:0)

RESERVED

(Stuffed with 0's)

The first bit (MSB) generated by STAC9704/7 is always stuffed with a 0. The following 7 bit

positions communicate the associated control register address, and the trailing 12 bit positions

are stuffed with 0's by STAC9704/7.

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