STAC9704 datasheet(12/49 Pages) HYNIX

12 / 49 page

SigmaTel, Inc.

STAC9704/7

10/02/98

2.1 Clocking

STAC9704/7 derives its clock internally from an externally connected 24.576 MHz crystal or an

oscillator through the XTAL_IN pin. Synchronization with the AC’97 controller is achieved through

the BIT_CLK pin at 12.288 MHz (half of crystal frequency).

The beginning of all audio sample packets, or “Audio Frames”, transferred over AC-link is

synchronized to the rising edge of the “SYNC” signal driven by the AC’97 controller.

Data is

transitioned on AC-link on every rising edge of BIT_CLK, and subsequently sampled by the receiving

side on each immediately following falling edge of BIT_CLK.

2.2 Reset

There are 3 types of resets as detailed under “Timing Characteristics”.

1. a “cold” reset where all STAC9704/7 logic and registers are initialized to their default state

2. a “warm” reset where the contents of the STAC9704/7 register set are left unaltered

3. a “register” reset which only initializes the STAC9704/7 registers to their default states

After signaling a reset to the STAC9704/7, the AC’97 controller should not attempt to play or capture

audio data until it has sampled a “Codec Ready” indication via register 26h from the STAC9704/7.

For proper reset operation, SDATA_OUT should be “0” during “cold” reset.

3. DIGITAL INTERFACE

3.1 AC-link Digital Serial Interface Protocol

The STAC9704/7 communicates to the AC’97 controller via a 5 pin digital serial interface called AC-

link, which is a bi-directional, fixed rate, serial PCM digital stream.

All digital audio streams,

commands and status information are communicated over this point to point serial interconnect. This

link handles multiple inputs, and output audio streams, as well as control register accesses using a time

division multiplexed (TDM) scheme. The AC’97 controller synchronizes all AC-link data transaction.

The following data streams are available on the STAC9704/7:

STAC9704 bảng dữ liệu(PDF) 12 Page - Hynix Semiconductor