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STAC9704 bảng dữ liệu(PDF) 14 Page - Hynix Semiconductor

tên linh kiện STAC9704
Giải thích chi tiết về linh kiện  Multimedia Audio Codec for AC97
PDF  49 Pages
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SigmaTel, Inc.
STAC9704/7
14
10/02/98
3.1.1 AC-link Audio Output Frame (SDATA_OUT)
The audio output frame data streams correspond to the multiplexed bundles of all digital output data
targeting the STAC9704/7 DAC inputs, and control registers. Each audio output frame supports up to
12 20-bit outgoing data time slots. Slot 0 is a special reserved time slot containing 16 bits that are used
for AC-link protocol infrastructure.
Within slot 0, the first bit is a global bit (SDATA_OUT slot 0, bit 15) which flags the validity for the
entire audio frame. If the “Valid Frame” bit is a 1, this indicates that the current audio frame contains
at least one slot time of valid data. The next 12 bit positions sampled by the STAC9704/7 indicate
which of the corresponding 12 times slots contain valid data. In this way data streams of differing
sample rates can be transmitted across AC-link at its fixed 48kHz audio frame rate. The following
diagram illustrates the time slot based AC-link protocol.
Figure 6. AC-link Audio Output Frame
SYNC
BIT_CLK
SDATA_OUT
valid
Frame
slot1
slot2
End of previous audio frame
slot(12) "0"
"0"
"0"
19
"0"
"0"
"0"
19
19
19
"0"
Data Phase
20.8 uS (48 kHZ)
Tag Phase
12.288 MHz
Time Slot "Valid" Bits
Slot 1
Slot 2
Slot 3
Slot 12
("1" = time slot contains valid PCM data)
A new audio output frame begins with a low to high transition of SYNC. SYNC is synchronous to the
rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK, the STAC9704/7
samples the assertion of SYNC. This following edge marks the time when both sides of AC-link are
aware of the start of a new audio frame. On the next rising edge of BIT_CLK, the AC’97 controller
transitions SDATA_OUT into the first bit position of slot 0 (Valid Frame bit). Each new bit position is
presented to AC-link on a rising edge of BIT_CLK, and subsequently sampled by the STAC9704/7 on
the following falling edge of BIT_CLK. This sequence ensures that data transitions, and subsequent
sample points for both incoming and outgoing data streams are time aligned.



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