STAC9704 datasheet(19/49 Pages) HYNIX

19 / 49 page

SigmaTel, Inc.

STAC9704/7

10/02/98

3.1.2.2 Slot 2: Status Data Port

The status data port delivers 16-bit control register read data.

Bit (19:4)

Control Register Read Data

(Stuffed with 0's if tagged "invalid")

Bit (3 :0)

RESERVED

(Stuffed with 0's)

If Slot 2 is tagged "invalid" by STAC9704/7, then the entire slot will be stuffed with 0's.

3.1.2.3 Slot 3: PCM Record Left Channel

Audio input frame slot 3 is the left channel output of STAC9704/7 input MUX, post-ADC.

STAC9704/7 ADCs are implemented to support 18-bit resolution.

STAC9704/7 outputs its ADC data (MSB first), and stuffs any trailing non-valid bit positions

with 0's to fill out its 20-bit time slot.

3.1.2.4 Slot 4: PCM Record Right Channel

Audio input frame slot 4 is the right channel output of STAC9704/7 input MUX, post-ADC.

STAC9704/7 outputs its ADC data (MSB first), and stuffs any trailing non-valid bit positions

with 0's to fill out its 20-bit time slot.

3.1.2.5 Slots 5-12: Reserved

Audio input frame slots 5-12 are reserved for future use and are always stuffed with 0's.

3.2 AC-link Low Power Mode

The STAC9704/7’s AC-Link can be placed in the low power mode by programming Register 26h to the

appropriate value. SDATA_IN is held at a logic low voltage level. The BIT_CLK is held at logic high

after slot 2, in violation of the AC97 specification. This issue is detailed in the STAC9704 errata, and

has not caused customer problems. The AC’97 controller can wake up the STAC9704/7 by providing

the appropriate reset signals.

STAC9704 bảng dữ liệu(PDF) 19 Page - Hynix Semiconductor