GMS81C2012 datasheet(31/107 Pages) HYNIX

31 / 107 page

HYUNDAI MicroElectronics

GMS81C2012/GMS81C2020

MAR. 2000 Ver 1.00

8.3 Data Memory

Figure 8-8 shows the internal Data Memory space availa-

ble. Data Memory is divided into two groups, a user RAM

(including Stack) and control registers.

Figure 8-8 Data Memory Map

User Memory

The GMS81C20xx have 448

× 8 bits for the user memory

(RAM).

Control Registers

The control registers are used by the CPU and Peripheral

function blocks for controlling the desired operation of the

device. Therefore these registers contain control and status

bits for the interrupt system, the timer/ counters, analog to

digital converters and I/O ports. The control registers are in

address range of 0C0H to 0FFH.

Note that unoccupied addresses may not be implemented

on the chip. Read accesses to these addresses will in gen-

eral return random data, and write accesses will have an in-

determinate effect.

More detailed informations of each register are explained

in each peripheral section.

Note: Write only registers can not be accessed by bit ma-

nipulation instruction. Do not use read-modify-write instruc-

tion. Use byte manipulation instruction, for example “LDM”.

Example; To write at CKCTLR

LDM

CLCTLR,#09H ;Divide ratio(

÷16)

Stack Area

The stack provides the area where the return address is

saved before a jump is performed during the processing

routine at the execution of a subroutine call instruction or

the acceptance of an interrupt.

When returning from the processing routine, executing the

subroutine return instruction [RET] restores the contents of

the program counter from the stack; executing the interrupt

return instruction [RETI] restores the contents of the pro-

gram counter and flags.

The save/restore locations in the stack are determined by

the stack pointed (SP). The SP is automatically decreased

after the saving, and increased before the restoring. This

means the value of the SP indicates the stack location

number for the next save. Refer to Figure 8-4 on page 27.

User Memory

Control

Registers

or Stack Area

0000H

00BFH

00C0H

00FFH

0100H

01FFH

PAGE0

User Memory

PAGE1

When “G-flag=0”,

When “G-flag=1”

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