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IO13PDB0V0 bảng dữ liệu(PDF) 146 Page - Microsemi Corporation |
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IO13PDB0V0 bảng dữ liệu(HTML) 146 Page - Microsemi Corporation |
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146 / 197 page  Pin Descriptions 5- 32 R e v i sio n 1 2 U5 VCC33SDD0 VCC33SDD0 VCC33SDD0 U6 VCC15A VCC15A VCC15A U7 NC ABPS3 ABPS3 U8 NC ADC2 ADC2 U9 NC VCC33ADC0 VCC33ADC0 U10 GND15ADC0 GND15ADC1 GND15ADC1 U11 VCC33ADC0 VCC33ADC1 VCC33ADC1 U12 ADC10 ADC7 ADC7 U13 ABPS0 ABPS6 ABPS6 U14 GNDTM0 GNDTM1 GNDTM1 U15 SPI_1_CLK/GPIO_26 SPI_1_CLK/GPIO_26 SPI_1_CLK/GPIO_26 U16 SPI_0_CLK/GPIO_18 SPI_0_CLK/GPIO_18 SPI_0_CLK/GPIO_18 U17 SPI_0_SS/GPIO_19 SPI_0_SS/GPIO_19 SPI_0_SS/GPIO_19 U19 GND GND GND U21 SPI_1_DO/GPIO_24 SPI_1_DO/GPIO_24 SPI_1_DO/GPIO_24 V1 NC MAC_CLK MAC_CLK V3 GNDSDD0 GNDSDD0 GNDSDD0 V19 SPI_1_DI/GPIO_25 SPI_1_DI/GPIO_25 SPI_1_DI/GPIO_25 V21 VCCMSSIOB2 VCCMSSIOB2 VCCMSSIOB2 W1 PCAP PCAP PCAP W3 NCAP NCAP NCAP W4 ADC2 CM0 CM0 W5 ADC3 TM0 TM0 W6 ADC4 TM1 TM1 W7 NC ADC0 ADC0 W8 NC ADC3 ADC3 W9 NC GND33ADC0 GND33ADC0 W10 VCC15ADC0 VCC15ADC1 VCC15ADC1 W11 GND33ADC0 GND33ADC1 GND33ADC1 W12 ADC8 ADC5 ADC5 W13 CM0 CM3 CM3 Pin No. CS288 A2F060 Function A2F200 Function A2F500 Function Notes: 1. Shading denotes pins that do not have completely identical functions from density to density. For example, the bank assignment can be different for an I/O, or the function might be available only on a larger density device. 2. *: Indicates that the signal assigned to the pins as a CLKBUF/CLKBUF_LVPECL/CLKBUF_LVDS goes through a glitchless mux. In order for the glitchless mux to operate correctly, the signal must be a free-running clock signal. Refer to the ’Glitchless MUX’ section in the SmartFusion Microcontroller Subsystem User’s Guide for more details. |
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