CS494002 datasheet(46/100 Pages) CIRRUS

46 / 100 page

reason, the serial clock should default to low so

that eight transitions from low to high to low

will occur for each byte.

4) When all 4 data bytes have been transferred,

chip select should be raised to signify an end of

write. Once again it is crucial that the serial

clock transitions from high to low on the last bit

of the last byte before chip select is raised, or a

loss of data will occur.

5) If more data needs to be sent, the host must

verify that the HINBSY pin is low before it

sends more data to DSPC. Note the HINBSY

pin is available only on the 144 pin devices. A

µS byte to byte latency must be obeyed

during run time for the 100 pin devices.

The same write routine could be used to send a 4-

byte message or an entire application code image.

From a hardware perspective, communication must

be in 4-byte multiples.

6.1.2.2 Reading in SPI for DSPC

A read operation is necessary when DSPC signals

that it has data to be read. DSPC does this by

dropping its interrupt request line (INTREQ) low.

When reading from the device in SPI, the same

protocol will be used whether reading a single byte

or multiple bytes. The examples shown in this

document can be expanded to fit any read situation.

Figure 35, "SPI Read Flow Diagram for DSPC" on

page 46 shows a typical read sequence:

The following is a detailed description of an SPI

read sequence with DSPC.

1) An SPI read transaction is initiated by DSPC

dropping INTREQ, signaling that it has data to

be read.

2) The host responds by driving chip select (SCS)

low.

3) This is followed by a 7-bit address and the

read/write bit set high for a read. The address

for DSPC defaults to 1000001b. It is necessary

to clock this address in prior to any transfer in

order for DSPC to acknowledge the read. In

other words a byte of 0x83 should be clocked

into the device preceding any read. The 0x83

byte represents the 7 bit address 1000001b, and

the least significant bit set to 1 designates a

read.

4) After the falling edge of the serial control clock

(SCCLK) for the read/write bit, the data is

ready to be clocked out on the control data out

pin (CDOUT). Data clocked out by the host is

valid on the rising edge of SCCLK and data

transitions occur on the falling edge of SCCLK.

The serial clock should default to low so that

eight transitions from low to high to low will

occur for each byte.

INTREQ (LO W )?

INTREQ STILL LOW ?

SCS HIGH

SCS LO W

REA D 4 DA TA BYTES

W RITE ADD RESS BYTE

W ITH MODE BIT S ET TO

1FOR RE AD

Figure 35. SPI Read Flow Diagram for DSPC

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