CS494002 datasheet(16/100 Pages) CIRRUS

16 / 100 page

1.11 Switching Characteristics — Motorola® Host Slave Mode (DSPC)

(TA =25 °C; VDD, PLLVDD = 2.5 V; VDDSD = 3.3 V; CL =20pF)

Notes: 1. Certain timing parameters are normalized to the DSP clock, DCLKP, in nanoseconds. DCLKP =

1/DCLK. The DSP clock can be defined as follows:

Internal Clock Mode:

DCLK ~ 60MHz before and during boot, i.e. DCLKP ~ 16.6ns

DCLK ~ 86 MHz after boot, i.e. DCLKP ~ 11.6ns

It should be noted that DCLK for the internal clock mode is application specific. The application code

users guide should be checked to confirm DCLK for the particular application.

Parameter

Symbol

Min

Max

Unit

Address setup before CS and DS low

Tmas

DCLKP

Address hold time after CS and DS low

Tmah

DCLKP+15

Read

Delay between DS then CS low or CS then DS low

Tmcdr

Data valid after CS and RD low with R/W high

Tmdd

2*DCLKP+

CS and DS low for read

(Note 1)

Tmrpw

2*DCLKP

Data hold time after CS or DS high after read

Tmdhr

DCLKP+ 10

Data high-Z after CS or DS high low after read

Tmdis

2*DCLKP+

CS or DS high to CS and DS low for next read

(Note 1)

Tmrd

2*DCLKP+10

CS or DS high to CS and DS low for next write

(Note 1)

Tmrdtw

2*DCLKP+10

Write

Delay between DS then CS low or CS then DS low

Tmcdw

Data setup before CS or DS high

Tmdsu

2*DCLKP+10

CS and DS low for write

(Note 1)

Tmwpw

2*DCLKP

R/W setup before CS AND DS low

Tmrwsu

DCLKP

R/W hold time after CS or DS high

Tmrwhld

Data hold after CS or DS high

Tmdhw

DCLKP

CS or DS high to CS and DS low with R/W high for next read

(Note 1)

Tmwtrd

2*DCLKP+10

CS or DS high to CS and DS low for next write

(Note 1)

Tmwd

2*DCLKP+10

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