CS494002 datasheet(57/100 Pages) CIRRUS

57 / 100 page

Failure to do this may cause the DSP’s output

message buffer to overflow, corrupting any

pending outbound messages.

6.3 Parallel Host Communication for DSPC

The parallel host communication modes of DSPC

provide an 8-bit interface to the DSP. An Intel-style

parallel mode and a Motorola-style parallel mode

are supported. The host interface is implemented

using four communication registers within DSPC

as shown in Table 8, “Parallel Input/Output

Registers for DSPC,” on page 58. The HOSTMSG

Since there are only

eight data pins, only one byte can be transferred at

a time, but a full 32 bits are transferred in each read

or write to this register.

When the host is downloading code or configuring

the application code in DSPC, control messages

must be written to (and read from) the Host

Message register 32 bits at a time. The HINBSY

pin and the HINBSY bit in the Host Control

determine when DSPC can accept another 32-bit

word of control data. The HINBSY pin and the

HINBSY bit (in the Host Control register) go high

when the host writes 32 bits (4 bytes) to the

HOSTMSG register. The HINBSY pin and

HINBSY bit go low when DSPC reads the 32 bit

data from the register. The INTREQ pin goes low

and the HOUTRDY bit (in the Host Control

must be read by the host.

The HOSTDATA1 and HOSTDATA2 registers

are used strictly for the transfer of audio data to

DSPC. The host cannot read from these two

registers. Support of these registers is DSPC

application code specific, see the appropriate

Application Note for availability.

A detailed description for each parallel host mode

will now be given. The following information will

be provided for the Intel mode and Motorola mode:

•

The pins of DSPC which must be used for prop-

er communication

•

Flow diagram and description for a parallel

byte write

•

Flow diagram and description for a 32-bit word

(4-byte) write

•

Flow diagram and description for a parallel

byte read

•

Flow diagram and description for a 32-bit word

(4-byte) read

The four registers of DSPC’s parallel host mode are

not used identically. The algorithm used for

communicating with each register will be given as

a functional description, building upon the basic

read and write protocols defined in the Motorola

and Intel sections. The following will be covered:

•

Flow diagram and description for a control

write

•

Flow diagram and description for a control read

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