CS494002 datasheet(66/100 Pages) CIRRUS

66 / 100 page

now be described in detail.

1) The host must first drive the A1 and A0 register

address pins of DSPC with the address of the

desired Parallel I/O Register (A1=A0=0). Note

that only the Host Message register can be read

using 4-byte reads. The address must be

maintained for the duration of the read cycle,

and is latched on the falling edge of CS.

Host Message:

A[1:0]==00b.

2) The host indicates that this is a read cycle by

driving the R/W pin high.

3) The host initiates a read cycle by driving the CS

and DS pins low (bus must be tri-stated by this

time).

4) Once the data is valid (after waiting the

appropriate time specified in the timing

specifications), the host can read the most

significant

byte

(bits

31:24)

from

the

HDAT[7:0] pins of DSPC.

5) The host indicates the byte has been read by

driving DS high.

6) The host latches out the next byte by driving

DS low.

7) Once the data is valid (after waiting the

appropriate time specified in the timing

specifications), the host can read the next most

significant byte, BYTE_B (bits 23:16), of the

selected register from the HDAT[7:0] pins of

DSPC.

8) The host indicates the byte has been read by

driving DS high.

9) The host latches out the next byte by driving

DS low.

10) Once the data is valid (after waiting the

appropriate time specified in the timing

specifications), the host can read the next most

significant byte, BYTE_A (bits 15:8), of the

selected register from the HDAT[7:0] pins of

R/W (HIGH)

ADDRESS A PARALLEL I/O REGISTER

(A[1:0] SET APPROPRIATELY)

CS (HIGH)

CS (LOW)

DS (LOW)

READ MS_BYTE TO

HDAT[7:0]

DS (HIGH)

DS (LOW)

READ BYTE_B TO

HDAT[7:0]

DS (HIGH)

DS (LOW)

READ BYTE_A TO

HDAT[7:0]

DS (HIGH)

READ LS_BYTE TO

HDAT[7:0]

DS (HIGH)

DS (LOW)

Figure 49. Motorola Mode, 32-Bit (4-Byte) Read Flow

Diagram for DSPC

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