CS494002 datasheet(26/100 Pages) CIRRUS

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1.18 Switching Characteristics — Digital Audio Output

(TA =25 °C; VDD, PLLVDD = 2.5 V; VDDSD = 3.3 V; CL =20pF)

Notes: 1. DSPC has two Digital Audio Output modules having analogous signal names ending in 0 and 1. Both

DAO ports share a common MCLK but have independent SCLKs and LRCLKs.

2. Master mode timing specifications are characterized, not production tested.

3. Master mode is defined as the CS49400 driving both SCLK0, SCLK1, LRCLK0, and LRCLK1. When

MCLK is an input, it is divided to produce SCLK0, SCLK1, LRCLK0 and LRCLK1.

4. This timing parameter is defined from the non-active edge of SCLK0 and SCLK1. The active edge of

SCLK0 and SCLK1 is the point at which the data is valid.

5. Slave mode is defined as SCLK0, SCLK1, LRCLK0 and LRCLK1 driven by an external source.

Parameter

Symbol

Min

Max

Unit

MCLK period

Tmclk

MCLK duty cycle

SCLK0, SCLK1 period for Master or Slave mode

(Note 2)

Tsclk

SCLK0, SCLK1 duty cycle for Master or Slave mode

(Note 2)

Master Mode (Output A1 Mode)

(Note 2, 3)

SCLK0, SCLK1 delay from MCLK rising edge, MCLK as an

input

Tsdmi

LRCLK0, LRCLK1 delay from SCLK0, SCLK1 transition,

respectively

(Note 4)

Tlrds

AUDATA7–0 delay from SCLK0, SCLK1 transition

(Note 4)

Tadsm

Slave Mode (Output A0 Mode)

(Note 5)

Time from active edge of SCLK0, SCLK1 to LRCLK0, LRCLK1

transition

Tstlr

Time from LRCLK0, LRCLK1 transition to SCLK0, SCLK1

active edge

Tlrts

AUDATA7–0 delay from SCLK0, SCLK1 transition

(Note 4)

Tadss

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