CS4215 datasheet(25/52 Pages) CIRRUS

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Power Down Mode

Bringing the PDN pin high puts the CS4215 into

the power down mode. In this mode HEADC

and CMOUT will not supply current. Power

down will change all the control registers to the

reset state shown under each Control Time Slot

pin will follow the TSIN state with less than

10 ns delay.

After returning to normal operation from power

down, an offset calibration cycle must be exe-

cuted. Either bringing RESET low then high, or

updating the control registers, will cause an off-

set calibration cycle. In either case, a delay of

50 ms must occur after PDN goes low before

executing the offset calibration. This allows the

internal voltage reference time to settle.

LOOPBACK TEST MODES

The CS4215 contains three loopback modes that

may be used to test the codec. Two of the loop-

back test modes are designed to allow the host to

perform a self-test on the CS4215. The third

mode allows laboratory testing using external

equipment.

Host Self-Test Loopback Modes

Since the CS4215 is a mixed-signal device, it is

equipped with an internal register that will en-

able the host to perform a two-tiered test on

power-up or as needed. The loopback test is en-

abled by setting the Enable Loopback bit, ENL,

in control register 4. The first tier of loopback is

a digital-digital loopback, DD, which is selected

by clearing the DAD bit in control register 4 (see

SD O U T

D e code

Dig ita l-

A n a log-

Dig ita l

Loop back

Ga in

A tte n uatio n

D/A

A/D

D ig ita l-D igita l

Loopbac k

SDIN

LO U T

RO U T

LIN

RIN

DA D

C S 4215

SD O U T

Dec od e

Ga in

A tte n ua tio n

D/A

A/D

E n code

SDIN

LO U T

RO U T

LIN

RIN

C S 4215

M onito r = 0

AD A

M onito r = 1111

(Full M ute)

(S till O perate)

(D isc onnec ted)

(D A C d a ta = 0 )

0 is diffe rent fo r

ea ch da ta

format

E n code

Figure 16. DD, DAD & ADA Loopback Paths

CS4215

DS76F2

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