CS4215 datasheet(11/52 Pages) CIRRUS

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after power up. A calibration cycle will occur

immediately after leaving the reset state. A cali-

bration cycle will also occur immediately after

going from control mode to data mode (D/C go-

ing high). When powering up the CS4215, or

exiting the power down state, a minimum of

50 ms must occur, to allow the voltage reference

to settle, before initiating a calibration cycle.

This is achieved by holding RESET low or stay-

ing in control mode for 50 ms after power up or

exiting power down mode. The input offset error

will be calibrated for whichever input channel is

selected (microphone or line, using the IS bit).

Therefore, the IS bit should remain steady while

the codec is calibrating, although the other bits

input to the codec are ignored. Calibration takes

194 FSYNC cycles and SDOUT data bits will be

zero during this period. The A/D Invalid bit, ADI

(bit 7 in data time slot 6), will be high during

calibration and will go low when calibration is

finished.

Parallel Input/Output

Two pins are provided for parallel input/output.

These pins are open drain outputs and require

external pull-up resistors. Writing a zero turns on

the output transistor, pulling the pin to ground;

writing a one turns off the output transistor,

which allows an external resistor to pull the pin

high. When used as an input, a one must be writ-

ten to the pin, thereby allowing an external

device to pull it low or leave it high. These pins

can be read in control mode and their state is

recorded in Control Register 5. These pins can

be written to and read back in data mode using

Data Register 7. Figure 5 shows the Parallel In-

put/Output timing.

Notes:

4. CONTROL MODE READ - The PIO pins are sampled by a rising edge of SCLK.

3. DATA MODE READ, WRITE - are tied to the rising edge of FSYNC and CLKOUT.

They are independent of SCLK.

2. CONTROL MODE READ - The data is sent out, via SDOUT, the same frame.

DATA MODE READ - The data is sent out via SDOUT on the next frame.

Data Mode -Read and Write

Control Mode - Read Only

TSIN

SCLK

1 SCLK

PIO Read

PIO Write

8.5 CLKOUT's

11 CLKOUT's

SCLK

CLKOUT

FSYNC

Figure 5. PIO Pin Timing

CS4215

DS76F2

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