A3P030 datasheet(91/220 Pages) MICROSEMI

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ProASIC3 Flash Family FPGAs

Revision 13

2-77

Timing Characteristics

Figure 2-20 • Input DDR Timing Diagram

tDDRICLR2Q2

tDDRIREMCLR

tDDRIRECCLR

tDDRICLR2Q1

CLK

Data

CLR

Out_QR

Out_QF

tDDRICLKQ1

tDDRIHD

tDDRISUD

tDDRICLKQ2

Table 2-102 • Input DDR Propagation Delays

Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V

Parameter

Description

–2

–1

Std.

Units

tDDRICLKQ1

Clock-to-Out Out_QR for Input DDR

0.27

0.31

0.37

tDDRICLKQ2

Clock-to-Out Out_QF for Input DDR

0.39

0.44

0.52

tDDRISUD

Data Setup for Input DDR (Fall)

0.25

0.28

0.33

Data Setup for Input DDR (Rise)

0.25

0.28

0.33

tDDRIHD

Data Hold for Input DDR (Fall)

0.00

Data Hold for Input DDR (Rise)

0.00

tDDRICLR2Q1

Asynchronous Clear-to-Out Out_QR for Input DDR

0.46

0.53

0.62

tDDRICLR2Q2

Asynchronous Clear-to-Out Out_QF for Input DDR

0.57

0.65

0.76

tDDRIREMCLR

Asynchronous Clear Removal time for Input DDR

0.00

tDDRIRECCLR

Asynchronous Clear Recovery time for Input DDR

0.22

0.25

0.30

tDDRIWCLR

Asynchronous Clear Minimum Pulse Width for Input DDR

0.22

0.25

0.30

tDDRICKMPWH Clock Minimum Pulse Width High for Input DDR

0.36

0.41

0.48

tDDRICKMPWL Clock Minimum Pulse Width Low for Input DDR

0.32

0.37

0.43

FDDRIMAX

Maximum Frequency for Input DDR

350

309

263

MHz

Note: For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-6 for derating values.

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