A3P030 datasheet(89/220 Pages) MICROSEMI

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ProASIC3 Flash Family FPGAs

Revision 13

2-75

Timing Characteristics

Table 2-100 • Output Enable Register Propagation Delays

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter

Description

–2

–1

Std. Units

tOECLKQ

Clock-to-Q of the Output Enable Register

0.59 0.67 0.79

tOESUD

Data Setup Time for the Output Enable Register

0.31 0.36 0.42

tOEHD

Data Hold Time for the Output Enable Register

0.00 0.00 0.00

tOESUE

Enable Setup Time for the Output Enable Register

0.44 0.50 0.58

tOEHE

Enable Hold Time for the Output Enable Register

0.00 0.00 0.00

tOECLR2Q

Asynchronous Clear-to-Q of the Output Enable Register

0.67 0.76 0.89

tOEPRE2Q

Asynchronous Preset-to-Q of the Output Enable Register

0.67 0.76 0.89

tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register

0.00 0.00 0.00

tOERECCLR

Asynchronous Clear Recovery Time for the Output Enable Register

0.22 0.25 0.30

tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register

0.00 0.00 0.00

tOERECPRE

Asynchronous Preset Recovery Time for the Output Enable Register

0.22 0.25 0.30

tOEWCLR

Asynchronous Clear Minimum Pulse Width for the Output Enable Register

0.22 0.25 0.30

tOEWPRE

Asynchronous Preset Minimum Pulse Width for the Output Enable Register 0.22 0.25 0.30

tOECKMPWH Clock Minimum Pulse Width High for the Output Enable Register

0.36 0.41 0.48

tOECKMPWL Clock Minimum Pulse Width Low for the Output Enable Register

0.32 0.37 0.43

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

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