VMV3 datasheet(13/212 Pages) MICROSEMI

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Military ProASIC3/EL Low Power Flash FPGAs

Revision 3

1-7

The CCC block has these key features:

•

Wide input frequency range (fIN_CCC) = 1.5 MHz up to 250 MHz

•

Output frequency range (fOUT_CCC) = 0.75 MHz up to 250 MHz

•

2 programmable delay types for clock skew minimization

•

Clock frequency synthesis

Additional CCC specifications:

•

Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output divider

configuration.

•

Output duty cycle = 50% ± 1.5% or better

•

Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single global

network used

•

Maximum acquisition time is 300 µs

•

Exceptional tolerance to input period jitter—allowable input jitter is up to 1.5 ns

•

Four precise phases; maximum misalignment between adjacent phases of 40 ps × 250 MHz /

fOUT_CCC

Global Clocking

Military ProASIC3/EL devices have extensive support for multiple clocking domains. In addition to the

CCC and PLL support described above, there is a comprehensive global clock distribution network.

Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant

global networks. The VersaNets can be driven by the CCC or directly accessed from the core via

multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid

distribution of high-fanout nets.

I/Os with Advanced I/O Standards

The military ProASIC3/EL family of FPGAs features a flexible I/O structure, supporting a range of

voltages (1.5 V, 1.8 V, 2.5 V, and 3.3 V). In addition, 1.2 V I/O operation is supported for military

ProASIC3EL devices. Military ProASIC3/EL FPGAs support different I/O standards, including single-

ended, differential, and voltage-referenced (military ProASIC3EL). The I/Os are organized into banks,

with two, four, or eight (military ProASIC3EL only) banks per device. The configuration of these banks

determines the I/O standards supported. For military ProASIC3EL, each I/O bank is subdivided into VREF

minibanks, which are used by voltage-referenced I/Os. VREF minibanks contain 8 to 18 I/Os. All the I/Os

in a given minibank share a common VREF line. Therefore, if any I/O in a given VREF minibank is

configured as a VREF pin, the remaining I/Os in that minibank will be able to use that reference voltage.

Each I/O module contains several input, output, and enable registers. These registers allow the

implementation of the following:

•

Single-data-rate applications (e.g., PCI 66 MHz, bidirectional SSTL 2 and 3, Class I and II)

•

Double-data-Rate applications (e.g., DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point

communications, and DDR 200 MHz SRAM using bidirectional HSTL Class II).

Military ProASIC3EL banks support LVPECL, LVDS, B-LVDS, and M-LVDS. B-LVDS and M-LVDS can

support up to 20 loads.

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