VMV3 datasheet(41/212 Pages) MICROSEMI

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Military ProASIC3/EL Low Power Flash FPGAs

Revision 3

2-27

Summary of I/O Timing Characteristics – Default I/O Software Settings

Table 2-28 • Summary of AC Measuring Points

Standard

Input/Output

Supply Voltage

Input Reference

Voltage (VREF_TYP)

Board Termination

Voltage (VTT_REF)

Measuring Trip

Point (Vtrip)

3.3 V LVTTL /

3.3 V LVCMOS

3.30 V

–

1.4 V

3.3 V LVCMOS Wide Range

3.30 V

–

1.4 V

2.5 V LVCMOS

2.50 V

–

1.2 V

1.8 V LVCMOS

2.50 V

–

0.90 V

1.5 V LVCMOS

1.80 V

–

0.75 V

1.2 V LVCMOS*

1.50 V

–

0.6 V

1.2 V LVCMOS Wide Range*

1.20 V

–

0.6 V

3.3 V PCI

1.20 V

–

0.285 * VCCI (RR)

3.30 V

–

0.615 * VCCI (FF))

3.3 V PCI-X

3.30 V

–

0.285 * VCCI (RR)

3.30 V

–

0.615 * VCCI (FF)

3.3 V GTL

2.50 V

0.8 V

1.2 V

VREF

2.5 V GTL

3.30 V

0.8 V

1.2 V

VREF

3.3 V GTL+

2.50 V

1.0 V

1.5 V

VREF

2.5 V GTL+

1.50 V

1.0 V

1.5 V

VREF

HSTL (I)

1.50 V

0.75 V

VREF

HSTL (II)

3.30 V

0.75 V

VREF

SSTL2 (I)

3.30 V

1.25 V

VREF

SSTL2 (II)

2.50 V

1.25 V

VREF

SSTL3 (I)

2.50 V

1.5 V

1.485 V

VREF

SSTL3 (II)

2.50 V

1.5 V

1.485 V

VREF

LVDS

3.30 V

–

Cross point

LVPECL

–

Cross point

Note:

*Applicable to A3PE600L and A3PE3000L devices operating at 1.2 V core regions only.

Table 2-29 • I/O AC Parameter Definitions

Parameter

Parameter Definition

tDP

Data to Pad delay through the Output Buffer

tPY

Pad to Data delay through the Input Buffer

tDOUT

Data to Output Buffer delay through the I/O interface

tEOUT

Enable to Output Buffer Tristate Control delay through the I/O interface

tDIN

Input Buffer to Data delay through the I/O interface

tHZ

Enable to Pad delay through the Output Buffer—High to Z

tZH

Enable to Pad delay through the Output Buffer—Z to High

tLZ

Enable to Pad delay through the Output Buffer—Low to Z

tZL

Enable to Pad delay through the Output Buffer—Z to Low

tZHS

Enable to Pad delay through the Output Buffer with delayed enable—Z to High

tZLS

Enable to Pad delay through the Output Buffer with delayed enable—Z to Low

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