VMV3 datasheet(85/212 Pages) MICROSEMI

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Military ProASIC3/EL Low Power Flash FPGAs

Revision 3

2-71

1.2 V LVCMOS Wide Range

Table 2-109 • Minimum and Maximum DC Input and Output Levels

Applicable to Pro I/O Banks for A3PE600L and A3PE3000L Operating at 1.2 V Core Voltage

1.2 V

LVCMOS

Wide Range1

Equiv.

Software

Default

Drive

Strength

Option2

VIL

VIH

VOL

VOH

IOL IOH IOSH IOSL IIL3 IIH4

Drive

Strength

Min.

Max.

Min.

Max.

Min.

VµA µA

Max.

mA5

Max.

mA5 µA6 µA6

100 µA

2 mA

–0.3 0.3 * VCCI 0.7 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 100 100 TBD TBD 15 15

Notes:

1. Applicable to A3PE600L and A3PE3000L devices only.

2. Note that 1.2 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will not operate at the

equivalent software default drive strength. These values are for normal ranges only.

3. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

4. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges

5. Currents are measured at 100°C junction temperature and maximum voltage.

6. Currents are measured at 125°C junction temperature.

7. Software default selection highlighted in gray.

Figure 2-14 • AC Loading

Table 2-110 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (Typ) (V)

CLOAD (pF)

01.2

0.6

–

Note:

*Measuring point = Vtrip. See Table 2-28 on page 2-27 for a complete table of trip points.

Test Point

Enable Path

Datapath

5 pF

R = 1 k

R to VCCI for tLZ / tZL / tZLS

R to GND for tHZ / tZH / tZHS

5 pF for tZH / tZHS / tZL / tZLS

5 pF for tHZ / tLZ

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