MPC8315CVRADDA datasheet(20/106 Pages) FREESCALE

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MPC8315E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

DDR and DDR2 SDRAM

This table provides the current draw characteristics for MVREF.

7.2

DDR and DDR2 SDRAM AC Electrical Characteristics

This section provides the AC electrical characteristics for the DDR and DDR2 SDRAM interface.

7.2.1

DDR and DDR2 SDRAM Input AC Timing Specifications

This table lists the input AC timing specifications for the DDR2 SDRAM (GVDD(typ) = 1.8 V).

This table lists the input AC timing specifications for the DDR SDRAM when GVDD(typ)=2.5 V.

The following two tables list the input AC timing specifications for the DDR SDRAM interface.

Delta input/output capacitance: DQ, DQS

CDIO

—0.5

Note:

1. This parameter is sampled. GVDD = 2.5 V ± 0.125 V, f = 1 MHz, TA =25C, VOUT = GVDD/2, VOUT (peak-to-peak) = 0.2 V.

Table 15. Current Draw Characteristics for MVREF

Parameter / Condition

Symbol

Min

Max

Unit

Note

Current draw for MVREF

IMVREF

—

500

A1

Note:

1. The voltage regulator for MVREF must be able to supply up to 500 A current.

Table 16. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface

At recommended operating conditions with GVDD of 1.8V ± 100 mV

Parameter

Symbol

Min

Max

Unit

Note

AC input low voltage

VIL

—

MVREF – 0.45

—

AC input high voltage

VIH

MVREF + 0.45

—

Table 17. DDR SDRAM Input AC Timing Specifications for 2.5 V Interface

At recommended operating conditions with GVDD of 2.5V ± 200 mV

Parameter

Symbol

Min

Max

Unit

Note

AC input low voltage

VIL

—

MVREF – 0.51

AC input high voltage

VIH

MVREF + 0.51

—

Table 18. DDR2 SDRAM Input AC Timing Specifications

At recommended operating conditions with GVDD of (1.8 V± 100 mV)

Parameter

Symbol

Min

Max

Unit

Note

Controller Skew for MDQS—MDQ

266 MHz

200 MHz

tCISKEW

–875

–1250

875

1250

1, 2, 3

Table 14. DDR SDRAM Capacitance for GVDD(typ) = 2.5 V Interface

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