MPC8315CVRADDA datasheet(55/106 Pages) FREESCALE

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MPC8315E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

High-Speed Serial Interfaces (HSSI)

between 100 mV and 400 mV. Figure 40 shows the SerDes reference clock input requirement

for DC-coupled connection scheme.

— For external AC-coupled connection, there is no common mode voltage requirement for the

clock driver. Since the external AC-coupling capacitor blocks the DC level, the clock driver

and the SerDes reference clock receiver operate in different command mode voltages. The

SerDes reference clock receiver in this connection scheme has its common mode voltage set to

XCOREVSS. Each signal wire of the differential inputs is allowed to swing below and above

the common mode voltage (XCOREVSS). Figure 41 shows the SerDes reference clock input

requirement for AC-coupled connection scheme.

•

Single-ended Mode

— The reference clock can also be single-ended. The SD_REF_CLK input amplitude

(single-ended swing) must be between 400mV and 800mV peak-peak (from Vmin to Vmax)

with SD_REF_CLK either left unconnected or tied to ground.

— The SD_REF_CLK input average voltage must be between 200 and 400 mV. Figure 42 shows

the SerDes reference clock input requirement for single-ended signaling mode.

— To meet the input amplitude requirement, the reference clock inputs might need to be DC or

AC-coupled externally. For the best noise performance, the reference of the clock could be DC

or AC-coupled into the unused phase (SD_REF_CLK) through the same source impedance as

the clock input (SD_REF_CLK) in use.

Figure 40. Differential Reference Clock Input DC Requirements (External DC-Coupled)

Figure 41. Differential Reference Clock Input DC Requirements (External AC-Coupled)

SD_REF_CLK

Vmax < 800 mV

Vmin > 0 V

100 mV < Vcm < 400 mV

200 mV < Input Amplitude or Differential Peak < 800 mV

SD_REF_CLK

Vcm

200 mV < Input Amplitude or Differential Peak < 800 mV

Vmax < Vcm + 400 mV

Vmin > Vcm – 400 mV

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