MPC8315CVRADDA datasheet(64/106 Pages) FREESCALE

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MPC8315E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

PCI Express

16.4.2

Transmitter Compliance Eye Diagrams

The TX eye diagram in Figure 50 is specified using the passive compliance/test measurement load (see

Figure 52) in place of any real PCI Express interconnect + RX component. There are two eye diagrams

that must be met for the transmitter. Both diagrams must be aligned in time using the jitter median to locate

the center of the eye diagram. The different eye diagrams differ in voltage depending on whether it is a

transition bit or a de-emphasized bit. The exact reduced voltage level of the de-emphasized bit is always

relative to the transition bit.

The eye diagram must be valid for any 250 consecutive UIs.

A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is

created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX

UI.

NOTE

It is recommended that the recovered TX UI be calculated using all edges in

the 3500 consecutive UI interval with a fit algorithm using a minimization

merit function (that is, least squares and median deviation fits).

Figure 50. Minimum Transmitter Timing and Voltage Output Compliance Specifications

[De-emphasized Bit]

566 mV (3 dB) >= VTX-DIFFp-p-MIN >= 505 mV (4 dB)

[Transition Bit]

VTX-DIFFp-p-MIN = 800 mV

[Transition Bit]

VTX-DIFFp-p-MIN = 800 mV

0.7 UI = UI – 0.3 UI(JTX-TOTAL-MAX)

VTX-DIFF = 0 mV

(D+ D– Crossing Point)

VTX-DIFF = 0 mV

(D+ D– Crossing Point)

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