MPC8315CVRADDA datasheet(61/106 Pages) FREESCALE

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MPC8315E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

PCI Express

16 PCI Express

This section describes the DC and AC electrical specifications for the PCI Express bus of the MPC8315E.

16.1

DC Requirements for PCI Express SD_REF_CLK and

SD_REF_CLK

For more information, see Section 15.2, “SerDes Reference Clocks.”

16.2

AC Requirements for PCI Express SerDes Clocks

This table lists the PCI Express SerDes clock AC requirements.

16.3

Clocking Dependencies

The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm)

of each other at all times. This is specified to allow bit rate clock sources with a ±300 ppm tolerance.

16.4

Physical Layer Specifications

Following is a summary of the specifications for the physical layer of PCI Express on this device. For

further details as well as the specifications of the transport and data link layer please use the PCI Express

Base Specification, Rev. 1.0a.

16.4.1

Differential Transmitter (TX) Output

This table defines the specifications for the differential output at all transmitters (TXs). The parameters are

specified at the component pins.

Table 53. SD_REF_CLK and SD_REF_CLK AC Requirements

Symbol

Parameter Description

Min

Typ

Max

Unit

Note

tREF

REFCLK cycle time

—

tREFCJ

REFCLK cycle-to-cycle jitter. Difference in the period of any two adjacent

REFCLK cycles.

——

100

—

tREFPJ

Phase jitter. Deviation in edge location with respect to mean edge location.

–50

—

Table 54. Differential Transmitter (TX) Output Specifications

Parameter

Symbol

Comments

Min

Typical

Max

Unit

Note

Unit interval

Each UI is 400 ps ± 300 ppm. UI does not

account for Spread Spectrum Clock

dictated variations.

399.88

400

400.12

Differential peak-to-peak

output voltage

VTX-DIFFp-p

VTX-DIFFp-p = 2*|VTX-D+ - VTX-D-|

0.8

—

1.2

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