MPC8315CVRADDA datasheet(12/106 Pages) FREESCALE

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MPC8315E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

Electrical Characteristics

3.2

Power Sequencing

The MPC8315E does not require the core supply voltage (VDD and VDDC) and I/O supply voltages

(GVDD, LVDDx_ON, LVDDx_OFF, NVDDx_ON and NVDDx_OFF) to be applied in any particular

order. During the power ramp up, before the power supplies are stable, if the I/O voltages are supplied

before the core voltage, there may be a period of time when all input and output pins be actively driven

and cause contention and/or excessive current. In order to avoid actively driving the I/O pins and to

eliminate excessive current draw, apply the continuous core voltage (VDDC) before the continuous I/O

voltages (LVDDx_ON and NVDDx_ON) and switchable core voltage (VDD) before the switchable I/O

voltages (GVDD, LVDDx_OFF, and NVDDx_OFF). PORESET should be asserted before the continuous

power supplies fully ramp up. In the case where the core voltage is applied first, the core voltage supply

must rise to 90% of its nominal value before the I/O supplies reach 0.7 V, see Figure 3. Once all the power

supplies are stable, wait for a minimum of 32 clock cycles before negating PORESET.

The I/O power supply ramp-up slew rate should be slower than 4V/100 s, this requirement is for ESD

circuit.

This figure shows the power-up sequencing for switchable and continuous supplies.

Figure 3. Power-Up Sequencing

When switching from normal mode to D3 warm (standby) mode, first turn off the switchable I/O voltage

supply and then turn off the switchable core voltage supply. Similarly, when switching from D3 warm

(standby) mode to normal mode, first turn on the switchable core voltage supply and then turn on the

switchable I/O voltage supply.

DUART, system control, I2C, JTAG,SPI

NVDD = 3.3 V

GPIO signals

NVDD = 3.3 V

eTSEC

LVDD = 3.3 V / 2.5 V

1 Output Impedance can also be adjusted through configurable options in DDR

Control Driver Register (DDRCDR). See the MPC8315E PowerQUICC II Pro

Integrated Host Processor Family Reference Manual.

Table 3. Output Drive Capability (continued)

Driver Type

Output

Impedance (

)

Supply

Voltage

Continuous I/O Voltage

Continuous Core Voltage

0.7 V

90%

Switchable I/O Voltage

Switchable Core Voltage (VDD)

0.7 V

90%

Power sequence for continuous power supplies

Power sequence for switchable power supplies

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