MPC8315CVRADDA datasheet(60/106 Pages) FREESCALE

60 / 106 page

MPC8315E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

High-Speed Serial Interfaces (HSSI)

Figure 48. Single-Ended Measurement Points for Rise and Fall Time Matching

The other detailed AC requirements of the SerDes Reference Clocks is defined by each interface protocol

based on application usage. Refer to the following sections for detailed information:

•

Section 9.5.2, “AC Requirements for SGMII SD_REF_CLK and SD_REF_CLK”

•

Section 16.2, “AC Requirements for PCI Express SerDes Clocks”

15.2.4.1

Spread Spectrum Clock

SD_REF_CLK/SD_REF_CLK are not intended to be used with, and should not be clocked by, a spread

spectrum clock source.

15.3

SerDes Transmitter and Receiver Reference Circuits

This figure shows the reference circuits for SerDes data lane’s transmitter and receiver.

Figure 49. SerDes Transmitter and Receiver Reference Circuits

The DC and AC specification of SerDes data lanes are defined in each interface protocol section below

(PCI Express or SGMII) in this document based on the application usage:

•

Section 9.5, “SGMII Interface Electrical Characteristics”

•

Section 16, “PCI Express”

Note that external AC Coupling capacitor is required for the above two serial transmission protocols with

the capacitor value defined in specification of each protocol section.

SDn_REF_CLK



Receiver

Transmitter

TXn

RXn



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