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PIC16F87 bảng dữ liệu(PDF) 16 Page - Microchip Technology |
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PIC16F87 bảng dữ liệu(HTML) 16 Page - Microchip Technology |
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16 / 230 page  PIC16F87/88 DS30487D-page 16 2002-2013 Microchip Technology Inc. Bank 2 100h(2) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 26, 135 101h TMR0 Timer0 Module Register xxxx xxxx 69 102h(2) PCL Program Counter’s (PC) Least Significant Byte 0000 0000 135 103h(2) STATUS IRP RP1 RP0 TO PD ZDC C 0001 1xxx 17 104h(2) FSR Indirect Data Memory Address Pointer xxxx xxxx 135 105h WDTCON — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000 142 106h PORTB PORTB Data Latch when written; PORTB pins when read (PIC16F87) PORTB Data Latch when written; PORTB pins when read (PIC16F88) xxxx xxxx 00xx xxxx 58 107h — Unimplemented — — 108h — Unimplemented — — 109h — Unimplemented — — 10Ah(1,2) PCLATH — — — Write Buffer for the Upper 5 bits of the Program Counter ---0 0000 135 10Bh(2) INTCON GIE PEIE TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 19, 69, 77 10Ch EEDATA EEPROM/Flash Data Register Low Byte xxxx xxxx 34 10Dh EEADR EEPROM/Flash Address Register Low Byte xxxx xxxx 34 10Eh EEDATH — — EEPROM/Flash Data Register High Byte --xx xxxx 34 10Fh EEADRH — — — — EEPROM/Flash Address Register High Byte ---- xxxx 34 Bank 3 180h(2) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 135 181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 18, 69 182h(2) PCL Program Counter (PC) Least Significant Byte 0000 0000 135 183h(2) STATUS IRP RP1 RP0 TO PD ZDC C 0001 1xxx 17 184h(2) FSR Indirect Data Memory Address Pointer xxxx xxxx 135 185h — Unimplemented — — 186h TRISB PORTB Data Direction Register 1111 1111 58, 83 187h — Unimplemented — — 188h — Unimplemented — — 189h — Unimplemented — — 18Ah(1,2) PCLATH — — — Write Buffer for the Upper 5 bits of the Program Counter ---0 0000 135 18Bh(2) INTCON GIE PEIE TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 19, 69, 77 18Ch EECON1 EEPGD — — FREE WRERR WREN WR RD x--x x000 28, 34 18Dh EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- 34 18Eh — Reserved, maintain clear 0000 0000 — 18Fh — Reserved, maintain clear 0000 0000 — TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Details on page Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8>, whose contents are transferred to the upper byte of the program counter. 2: These registers can be addressed from any bank. 3: RA5 is an input only; the state of the TRISA5 bit has no effect and will always read ‘1’. 4: PIC16F88 device only. |
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