PIC16F87 datasheet(49/230 Pages) MICROCHIP

49 / 230 page

 2002-2013 Microchip Technology Inc.

DS30487D-page 49

PIC16F87/88

TABLE 4-4:

CLOCK SWITCHING MODES

Current

System

Clock

SCS Bits <1:0>

Modified to:

Delay

OSTS

Bit

IOFS

Bit

T1RUN

Bit

New

System

Clock

Comments

LP, XT, HS,

T1OSC,

EC, RC

(INTRC)

FOSC<2:0> = LP,

XT or HS

8 Clocks of

INTRC

01(1)

INTRC

INTOSC

Postscaler

The internal RC oscillator

frequency is dependant upon

the IRCF bits.

LP, XT, HS,

INTRC,

EC, RC

(T1OSC)

FOSC<2:0> = LP,

XT or HS

8 Clocks of

T1OSC

N/A

T1OSC

T1OSCEN bit must be

enabled.

INTRC

T1OSC

FOSC<2:0> = EC

FOSC<2:0> = RC

8 Clocks of

N/A

INTRC

T1OSC

FOSC<2:0> = LP,

XT, HS

1024 Clocks

(OST)

8 Clocks of

LP, XT, HS

N/A

LP, XT, HS During the 1024 clocks,

program execution is clocked

from the secondary oscillator

until the primary oscillator

becomes stable.

LP, XT, HS

(Due to Reset)

LP, XT, HS

1024 Clocks

(OST)

N/A

LP, XT, HS When a Reset occurs, there is

no clock transition sequence.

Instruction execution and/or

peripheral operation is

suspended unless Two-Speed

Start-up mode is enabled, after

which the INTRC will act as the

system clock until the OST

timer has expired.

Note 1: If the new clock source is the INTOSC or INTOSC postscaler, then the IOFS bit will be set 4 ms (approx.)

after the clock change.

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